`timescale 10ns/1ps

module RF_test;
	reg [4:0] Read1, Read2, Write; 
	reg [7:0] WriteData;
	reg RegWrite, Clk, RESET;
	wire [7:0] Data1, Data2;
	
	RF U0(.*);
	
	initial begin
		Clk=1'b1;
		forever #0.5 Clk=~Clk;
	end
	
	initial fork
		Read2 <= 5'b00000;
		Write <= 5'b10101;
		Read1 <= 5'b10101;
		WriteData <= 8'b11001100;
		{RegWrite, RESET} <= 2'b01;
		#1 RESET <= 1'b0;
		#5 RegWrite <= 1'b1;
		#6 RegWrite <= 1'b0;
		#10 {Write, WriteData, RegWrite, Read2} <= 19'b01000_01010101_1_01000;
		#11 RegWrite <= 1'b0;
		
		#20 {Write, WriteData, RegWrite, Read2} <= 19'b00000_11010101_1_00000;
		#21 RegWrite <= 1'b0;
	join
	
endmodule